Google launched four TPU systems within a year—the first time in the ten-year history of TPUs. Today, Amin Vahdat, head of Google AI and Infrastructure, on XAnnounceThe eighth-generation TPU product line adds two more models: TPU 8i Max boasts the largest context window and the highest compute density per rack, while TPU 8tx targets secure and confidential inference. With the 8t and 8i announced at Google Cloud Next in April this year, the eighth generation now has four systems in total, and Google Cloud also used a post to lay out the positioning of the four systems side by side.
New chip vs new system
Google wrote on its official blog: Designing a new chip means laying out billions of transistors on a wafer; constrained by the laws of physics and long manufacturing cycles, it takes years. Designing a new system means deciding how compute, networking, and storage are assembled around this chip, including the packaging method, so it can quickly respond to emerging customer needs. Among them, 8tx is “built on the same silicon as TPU 8t,” meaning it uses the 8t chip; 8i Max is “two low-latency TPU 8i chips … onto a single package,” with two 8i chips packaged in a single package.
Beneath the four systems are actually two chips. What Google has done over the past year is rapidly assemble four types of machines for different workloads from the same silicon chips, using different packaging, memory, networking, and security configurations. By Google’s own account, this approach can deliver purpose-built supercomputers in months rather than years.
8i Max: two 8i units sealed together
TPU 8i Max solves the memory wall. When dozens of AI agents simultaneously process an entire codebase or hours of video, memory bandwidth quickly becomes a bottleneck. The approach is straightforward: package two low-latency TPU 8i chips into the same package. Compute, SRAM, and HBM bandwidth double in sync, so the processor does not stall because it cannot get data. And because twice the silicon fits into existing rack space, compute per square foot and per watt in the data center can increase significantly.
In terms of positioning, the 8i Max targets a million-token-level context window. This requirement comes from agentic workloads: multiple AI agents need to reason simultaneously across an entire codebase or long videos, and traditional memory configurations cannot keep up. As a benchmark, the 8t and 8i launched in April cited figures at the time of up to 2.7x higher training performance and an 80% improvement in inference price-performance.
8tx: Confidential reasoning, but with one precondition.
TPU 8tx aims to provide hardware-level confidential computing. Normally, data is encrypted when stored or transmitted over networks, but it must be decrypted in memory when a computer processes it; what 8tx seeks to achieve is keeping even in-use data and model weights protected and isolated.
In terms of specifications, the 8tx uses the same 8t chip, paired with 5th Gen AMD EPYC processor hosts, and adopts the low-latency Boardfly network from the 8i. Official figures show latency reduced by up to 2x compared with the 8t, with near-zero performance loss. This combination lets enterprises fine-tune models with their own private data, distill large models into small models, and train agents with reinforcement learning on the same system, without having to move sensitive data between different clusters.
Software is the real focus this time.
Vahdat put it bluntly in the post: “Hardware is only as good as the software stack.” In this announcement, software actually takes up more space than hardware. TorchTPU was open-sourced last month; PyTorch code and Hugging Face models can now run natively on TPUs without rewriting code, and mainstream open-source inference engines such as vLLM and SGLang also have out-of-the-box TPU backends.
TPU Sync is the most technically sophisticated item this time. It is the model state layer of the TPU cluster, integrating chip HBM, host DRAM, shared storage, and the data center network into a single memory hierarchy. It can move large KV caches off-chip at millisecond-level speed, stream context between disaggregated prefill and decode nodes, and synchronize reinforcement learning weights. The official figures are more than 90% reduction in KV transfer latency and time to first token (TTFT).
Agent Compute Engine, by contrast, targets the characteristics of agentic workloads: AI agents are stateful and often pause to wait for database queries, external tools, or human feedback—stopping for anywhere from a few seconds to several hours. This software automatically suspends idle agent sessions, moving working memory off-chip in milliseconds to reduce operating costs.
There is also the XLA Serving Engine (Python training, C++ low-latency execution, across TPU/GPU/CPU), the TPU agent suite (which can connect to Claude Code, Cursor, and Google Antigravity to automatically complete TPU onboarding, bottleneck diagnosis, and kernel tuning using natural language), and Cloud Pathways with GKE dynamic slicing (using optical circuit switching to assemble or partition TPU topologies in real time, reducing job startup time by up to 5x and accelerating failure recovery by up to 4.5x).
Customer and Market Reaction
Google says TPU is now a fast-growing business with nearly 100 customers, spanning frontier labs, traders, retailers, and universities. On performance, it claims that the native vLLM-TorchTPU stack achieved the best price-performance ratio on two industry benchmarks, InferenceX and AgentX.
The community reaction offered a different perspective. Some users asked directly, “The chips are better, but AI models have actually gotten more expensive?” Others wondered whether this could improve the API’s long-standing overload error problem, and “Where are the new models?”
Conclusion
Google’s TPU strategy over the past year has a clear logic: chip iteration is slow, while system assembly is fast, so shift the focus of innovation to the system layer. The four systems correspond to four stages—training, low-latency inference, confidential computing, and ultra-large context—which amounts to equipping each stage of an agent’s entire lifecycle with a dedicated accelerator.
For developers, the barrier has always been migration cost; spec numbers are secondary. TorchTPU lets PyTorch code run on TPUs without rewriting, and this affects the decision of whether to use TPUs—an impact greater than any multiplier figure. Teams that want to evaluate it in practice can check available configurations directly on the Google Cloud TPU product page.
Source:Our newest TPUs
Source: KOCPC Chinese