Intel and AMD, rivals that have been head-to-head in the CPU market for decades, are continuing to deepen their cooperation through the x86 Ecosystem Advisory Group (EAG). Following the joint release of the ACE (AI Compute Extensions) AI matrix acceleration instruction set white paper two days ago, EAG once again revealed the latest details of APX (Advanced Performance Extensions). This instruction set expansion, called “the biggest evolution of x86 since 64-bit,” directly doubles the number of general-purpose registers and significantly improves performance without increasing chip area and power consumption.
What is APX? Why is x86 a big evolution?
APX (Advanced Performance Extensions) is a new generation x86 instruction set extension standard jointly developed by Intel and AMD. Its core ethos is very straightforward:Allow the x86 instruction set to access more registers (Registers)。
The temporary register is a storage unit with extremely small capacity inside the CPU but extremely fast access speed. It is responsible for storing the data, instructions and memory addresses being processed. When the instruction set can access more registers, the processor can complete more work in less time because large amounts of data can be processed directly within the CPU without the need to frequently read and write to slower memory.
This specification was announced by Intel as early as October 2024 proposed for the first time, now jointly promoted by Intel and AMD under the framework of EAG, and more technical details have been released.
APX six core improvements
APX is not a single feature enhancement, but a systematic upgrade to the x86 instruction set architecture. The following are the main improvement projects:
General Purpose Register (GPR) doubled: Expanded from the existing 16 to 32 in one fell swoop. This allows the compiler to retain more data and variables in the temporary register instead of writing to slower memory, which directly helps the efficiency of program code compilation and execution.
Improved memory operation efficiency: After simulation verification of the SPEC CPU 2017 integer benchmark test, the APX compiled program code can reduce 10% of read operations (loads) and 20% of write operations (stores), representing faster and lower power consumption program execution.
non-destructive command form: Traditional x86 instructions are mostly “destructive”, and the operation result will directly overwrite one of the source operands. APX has a new non-destructive version that reduces the need for register copies, making the code simpler and faster.
conditional execution extension: In the past, x86 conditional execution was limited to a few instructions such as CMOV and SET. APX has added conditional read (Conditional Load), conditional write (Conditional Store), conditional comparison/test (Conditional Compare/Test) and flag suppression functions, which greatly expands the application scope of if-conversion and reduces branch prediction errors.
Stacking operation enhancement: Added PUSH2 and POP2 instructions, which can push or pop up two temporary registers at the same time in one memory operation, speeding up the entry and return process of function calls.
Code density remains unchanged: Despite the large number of new instructions and functions, APX does not significantly increase the code size and is fully backwards compatible – existing x86 software can run seamlessly on processors that support APX.
It is a strategic layout under the same EAG framework as the ACE instruction set.
The timing of APX’s announcement is extremely strategic. Just two days ago, on April 30, Intel and AMD jointly released a technical white paper on ACE (AI Compute Extensions), positioning it as a “standard matrix acceleration architecture” for the x86 architecture. It supports mainstream AI data formats such as INT8, FP8, and BF16, and is compatible with the AVX10 instruction set.
ACE focuses on AI matrix operation acceleration, while APX focuses on the overall improvement of general computing performance: the two complement each other and together form EAG’s complete blueprint for the future development of the x86 architecture. Since its establishment last year, EAG has successively announced many core features such as FRED (Flexible Return and Event Delivery), AVX10 (Vector Instruction Set Unification), ChkTag (Memory Security Tag Check), and ACE and APX.
No need for larger area or higher power consumption, performance will naturally improve
One of the most amazing features of APX is that these performance improvements come at almost no cost in additional silicon area or power consumption. Wccftech’s report emphasizes that APX can achieve higher general computing performance without significantly increasing core area and power consumption: This is of great significance for chip design and cooling solutions.
What it means for developers and consumers
For software developers, the greatest value of APX is that the optimization space of the compiler is greatly increased. When the compiler can keep more variables in registers rather than in memory, programs can run faster and use less power. Especially for mainstream compilers such as LLVM and GCC, APX’s 32 general-purpose registers will become a very attractive compilation target.
For ordinary consumers, the benefits brought by APX will be indirectly reflected in daily use: from web browsing and word processing to gaming and content creation, APX-enabled processors will be able to complete the same work with lower power consumption, or provide smoother performance at the same power consumption.
Conclusion
Intel and AMD have gone from being competitors for decades to now joining forces under the EAG framework to promote the evolution of the x86 architecture: This is not only to combat the emerging threats of ARM and RISC-V, but also to inject new vitality into the x86 instruction set architecture that has lasted nearly half a century. APX’s doubling of general-purpose registers, ACE’s AI matrix acceleration standardization, coupled with a series of infrastructure innovations such as FRED, AVX10, ChkTag, etc., the x86 story is obviously not finished yet.
Source: KOCPC Chinese