Global DRAM prices continue to soar, and even the deep-pocketed Meta is starting to complain. At ISCA 2026 (International Symposium on Computer Architecture) held in Japan on June 29, Meta unveiled a custom ASIC chip of its own design, codenamed “Vistara,” which can bridge DDR4 memory modules removed from old servers for use in new-generation servers that only support DDR5, via the CXL protocol. This technology is expected to save Meta tens of millions of dollars in hardware procurement costs, while also reducing the demand for AI inference servers by up to 25%, which is particularly noteworthy given the current environment of persistently high memory prices.
Using DDR4 as DDR5! Meta Unveils Self-Developed Vistara Chip, Reusing Old Memory Saves Tens of Millions of Dollars
What is Vistara?
Vistara is Meta’s first-generation self-designed CXL (Compute Express Link) memory expansion ASIC chip. It acts as a bridge, connecting legacy DDR4 RDIMMs to next-generation servers powered by AMD EPYC “Turin” processors via PCIe Gen5 x16 interface and CXL 2.0/1.1 protocol. Each Vistara chip supports two independent 72-bit DDR4 memory channels, delivering a maximum capacity of 256GB (using 64GB DIMMs), while Meta’s current deployment uses 32GB DDR4 modules reclaimed from decommissioned servers, providing 128GB per chip.
Vistara’s core architecture is based on three RISC-V processor cores responsible for critical tasks including secure boot, device initialization, firmware management, and health monitoring. Meta states that its CXL controller and memory pipeline have been deeply optimized, reducing idle round-trip latency to approximately 50 nanoseconds (about 250 clock cycles), and supports Reed-Solomon dual-symbol error correction and x4 chip-kill protection, ensuring that reclaimed memory reliability is on par with new modules. The chip is manufactured using TSMC’s advanced process node, with detailed power consumption and die area data not yet publicly disclosed.
MemServer Architecture: Hybrid Operation Principles of New and Legacy Memory
Meta deploys Vistara chips in standalone units called “MemServer.” Each MemServer is equipped with two Vistara ASICs, connected via PCIe 5.0 x8 to a single 158-core AMD EPYC Turin processor. The final configuration consists of 768GB of native DDR5-6400 memory plus 256GB of reclaimed DDR4-2400 memory connected via the CXL interface, totaling approximately 1TB of capacity. From the operating system’s perspective, these two memory tiers are recognized as different NUMA nodes.
On the software side, the operating system automatically recognizes CXL memory as an additional NUMA node. The Linux kernel’s page migration mechanism moves less frequently accessed “cold data” to the slower DDR4 tier (with bandwidth of approximately 76 GB/s), while keeping frequently accessed hot data in the faster DDR5 tier (with bandwidth of approximately 614 GB/s). This design ensures that performance-sensitive workloads remain unaffected, while allowing idle legacy memory to deliver remaining value.
Why do we need to develop our own chips?
Meta didn’t hold back in its paper, laying out the pain point plainly: roughly 40% of the company’s server fleet can’t have its memory expanded. While DIMM modules can actually last 7 to 10 years, the server chassis they run in need to be replaced every 3 to 5 years. Tons of perfectly functional DDR4 memory gets scrapped along with the old machines, creating massive resource waste and cost burdens. The CXL hardware available on the market can’t solve this problem because it ties the memory controller and the memory itself together, preventing users from swapping out DIMMs on their own. Vistara completely separates the controller from the memory, allowing Meta to freely plug in whatever DDR4 modules it already has on hand, regardless of brand or model.
Results: AI inference servers reduced by 25%
According to data from Meta’s paper published at ISCA 2026 (note that these measurements were conducted by Meta and have not been verified by third parties), the Vistara architecture delivers three significant benefits:
- Demand for AI inference servers drops 25%Memory reclamation effectively alleviates memory capacity bottlenecks, allowing each server to handle more inference tasks.
- Task Restart with 33% Lower Resource Fragmentation OverheadThe CXL layer effectively reduces the frequency of Out of Memory (OOM) events.
- Supports mixed memory from multiple generationsEven in the future DDR6 era, the Vistara architecture can continue to support DDR5 and DDR4 memory, enabling cross-generational memory reuse.
Beyond Meta: The CXL Ecosystem Is Taking Shape
Meta is not the only company to present CXL memory solutions at ISCA 2026. Korean startup Panmnesia showcased its new CXL controller and Fabric Switch solution at the same Industry Session, supporting memory pool expansion of up to 64 nodes, and has entered the PCIe 7.0/CXL 4.0 IP development stage. Panmnesia CEO Myoungsoo Jung stated that early CXL implementations suffered from significant latency issues due to inheriting the PCIe architecture, and CXL switches were often considered unable to meet the latency requirements of memory access. However, the company’s next-generation architecture has fully overcome this limitation. Panmnesia’s Fusion Switch has entered the pre-release silicon stage.
This also highlights a noteworthy industry trend: hyperscalers with in-house chip development capabilities can bypass the impact of DRAM shortages by creating proprietary memory solutions, while other enterprises are left to endure price volatility from market fluctuations. CXL controller suppliers now have a highly compelling reference customer, and AMD’s EPYC Turin platform has gained a real-world memory expansion use case that previously only existed in presentations—a positive development for the entire server ecosystem.
Source: KOCPC Chinese