After Huawei presented the Tau (τ) Scaling Law (Tao’s Law) and LogicFolding architecture at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in May this year, it recently released the second version of its technical document, further detailing the actual engineering implementation of the related technologies, including specific process parameters such as hybrid bonding pitch, alignment accuracy, and TSV critical dimensions.
What is Hybrid Bonding and LogicFolding?
Huawei’s proposed “Tao’s Law” centers on shifting from traditional “geometric scaling” (shrinking transistor dimensions) to “temporal scaling” (reducing signal propagation delay τ). LogicFolding is precisely the key technology enabling this goal, folding originally planar logic circuits vertically into two active layers, like origami, then using hybrid bonding technology to tightly connect the upper and lower layers.
Hybrid bonding is an advanced packaging technology that enables direct copper-to-copper bonding at the wafer or chip level, without traditional micro-bumps, thereby significantly reducing the pitch of vertical interconnects. Huawei achieved a 1.5μm hybrid bonding pitch in the Kirin 2026, far superior to TSMC’s SoIC at less than 15μm and Intel’s Foveros at approximately 25μm TSV pitch. SemiAnalysis on thisReviewIn one fell swoop, China surpassed all competitors in advanced hybrid bonding technology.
By vertically stacking logic layers, the data transmission distance is reduced from the millimeter level of traditional planar designs to the micrometer level, significantly reducing signal propagation delay and power consumption while also improving bandwidth. Huawei pointed out in their paper that although the LogicFolding implementation in Kirin 2026 is still conservative, only selectively applied to critical paths with TSV landing advanced only to one layer below the top metal layer, it has already demonstrated significant performance improvements.
Kirin 2026 detailed technical specifications
According to data disclosed in the paper, the Kirin 2026 achieved the following breakthrough performance on SMIC’s 7nm-class DUV process through the LogicFolding architecture:
- transistor densityFrom 155 MTr/mm² to 238 MTr/mm², a jump of 53.5%, second only to TSMC’s 3nm node at approximately 40 MTr/mm²
- Energy efficiency improvementP-Cores deliver 41% higher energy efficiency
- Maximum clock speedUp to 3.1GHz, a 12.7% improvement over the previous generation
- SRAM PerformanceAccess speed and operating frequency increased by over 40%, with significantly reduced energy consumption per bit
- clock buffer: Reduce by over 50%
- Clock skewReduced by 25%
- wiring lengthReduce by about 30%
- Global Network-on-Chip data path area: 55% reduction
The paper also specifies concrete process constraints: the gear ratio between hybrid bonding pitch and top metal pitch should be less than 3, with closer to 1 being optimal; alignment accuracy must be better than 0.5μm; TSV critical dimension and keep-out zone must be less than 1.5μm; TSV pitch must be less than 6μm; failure rate must be below 100ppm, with smart redundancy mechanisms raising the repair rate to 99.9%, ultimately achieving near-100% yield.
Huawei’s chip performance roadmap
Huawei also unveiled the Kirin series performance evolution roadmap from 2023 to 2031, with the goal of continuously advancing through Tau scaling law.
- 2023：126 MTr/mm²，2.6GHz
- 2024：126 MTr/mm²，2.65GHz
- 2025：155 MTr/mm²，2.75GHz
- 2026238 MTr/mm², 3.1GHz ← Kirin 2026 (LogicFolding’s first mass-produced product)
- 2027：252 MTr/mm²，3.39GHz
- 2028：266 MTr/mm²，3.71GHz
- 2029：277 MTr/mm²，4.0GHz
- 2030：292 MTr/mm²，4.3GHz
- 2031400+ MTr/mm², 5.0GHz (equivalent to 1.4nm process level)
The first Kirin 2026 chip featuring the LogicFolding architecture is expected to launch in fall 2026, and will debut on Huawei’s Mate 90 series flagship smartphones.
Comparison with competitors’ packaging technology
Huawei is not the only company that has realized traditional packaging technology has become a performance bottleneck. Major chipmakers are all exploring their own advanced packaging solutions:
- Samsung Exynos 2700Separate the DRAM from the logic chip, and add a copper heat spreader block (Heat Pass Block) on top of the chip to enhance heat dissipation
- Apple A20 ProAdopts wafer-level multi-chip module (WMCM) packaging to enable the SoC to directly contact a large vapor chamber for efficient heat dissipation.
- TSMC SoICHybrid bonding pitch of less than 15μm for 3D chip stacking
- Intel FoverosApproximately 25μm TSV pitch for multi-chip 3D packaging
Huawei’s 1.5μm hybrid bonding pitch does lead on paper, but analysts also point out that Huawei achieves a doubling of transistor density by using twice the silicon area—this is fundamentally different from advanced EUV processes that deliver higher density directly on a smaller footprint. If the same stacking technology were applied to advanced EUV nodes, the leader’s advantage would only expand further.
From Kirin to Ascend: AI Systems Are the Real Strategic Battlefield
The paper also clearly points out that the successful application of LogicFolding on Kirin is only the first step, with the real strategic goal being AI data centers. Huawei’s Ascend AI accelerator series can also benefit from Tau’s scaling law, achieving higher compute density and energy efficiency at the same process node through 3D stacking and hybrid bonding technology.
Huawei has confirmed that its super node cluster performance will see a significant leap forward: the Atlas 950 delivers 8 EFLOPS, the Atlas 960 is expected to reach 60 EFLOPS by 2027, and the Atlas NEXT in 2030 will reach the ZFLOPS level, representing a 125x improvement over the previous generation.
Conclusion
Huawei’s hybrid bonding and LogicFolding technology essentially achieves performance improvements through advanced packaging and 3D stacking as a workaround, given the constraint of being unable to obtain EUV lithography equipment. This is not a “process breakthrough” in the traditional sense, but rather a system-level optimization strategy that shifts semiconductor performance competition from single manufacturing nodes to the comprehensive system efficiency of manufacturing, packaging, interconnect, architecture, and software.
Despite all the theory behind “Tao’s Law,” what ultimately matters is whether Huawei can actually deliver the performance numbers outlined in the paper with the Kirin 9050 processor that will power the Mate 90 series launching this fall, and whether the yield rate can reach mass production levels—this will be the key test of whether this technical route is viable. Recently, GeekBench released a review of the Kirin 9030 processor that Huawei has had on hold for over half a year, which feels like it’s setting the stage for the upcoming Kirin 9050 processor built on Tao’s Law (as a control group). Whether it can truly deliver the massive performance gains Huawei claims remains to be seen.
Source: KOCPC Chinese